In recent years, there is a growing need for a large-capacity storage system using a low-cost and high-density flash memory. To realize the large-capacity storage system, it is considered that more flash memories are connected. However, if more flash memories are connected, a signal (CE#) to select a chip and a signal (R/B#) to notify an operation state of the chip increase. When the numbers of these signals increase, signal lines of these signals increase and the number of pins in a memory controller increases. As a result, the package size becomes large and the cost becomes high.
Therefore, a configuration to reduce signal lines in a semiconductor device is required. The related art of the present technical field includes Patent Literature 1. Patent Literature 1 describes that “A semiconductor device comprises both a mode signal generating circuit 11 to generate a plurality of mode signals M0 to M2 corresponding to the operation modes of the semiconductor device, and a test signal generating circuit 12 to generate a plurality of test signals T0 to T2 for testing the semiconductor device in the operation modes corresponding to the generated mode signals M0 to M2. The semiconductor device transmits each of the mode signals M0 to M2 and the test signals T0 to T2 to predetermined regions via a plurality of signal conductors. In this case, an encoder circuit 16 to encode the mode signals M0 to M2 and the test signals T0 to T2, and to supply them to the signal conductors as encode signals S0 to S3 with the number of bits fewer than the sum of the number of bits of both the mode signals M0 to M2 and the test signals T0 to T2, is arranged” (see Abstract).